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Hardware Security Lab

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#40113 / #1

WS 2014/15 - WS 2015/16

English

Hardware Security Lab

6

Seifert, Jean-Pierre

benotet

Portfolioprüfung

Zugehörigkeit


Fakultät IV

Institut für Softwaretechnik und Theoretische Informatik

34355100 FG S-Professur Security in Telecommunications

No information

Kontakt


TEL 16

Saß, Marvin

lehre@sect.tu-berlin.de

https://tu.berlin/sect

Learning Outcomes

This module’s qualification aims are: 1. Thorough understanding of security relevant logic on modern integrated circuits. 2. Familiarity with different classes of hardware analysis techniques. 3. Design of purpose-built hardware analysis tools. 4. Hardware attack mitigation techniques and architectural improvements. The course is designed to impart: Technical skills: 50 % Method skills: 35 % System skills: 5 % Social skills: 10 %

Content

This module combines the theoretical “Hardware Security” lecture with the practical “Hardware Security Lab” course. The lecture will introduce students to common hardware analysis techniques including non-invasive, semi-invasive and fully-invasive IC analysis. Students will become familiarized with common pitfalls in secure hardware designs. The lecture will include reading and discussion of introductory material on the topic of hardware security. Though the lecture remains mostly theoretical, the Hardware Security Lab provides students hands-on experience with several low-level attacks. During the practical course students will have an opportunity to perform black box analysis of embedded devices and subsequently design custom hardware analysis tools capable of exploiting vulnerabilities in their implementation. Through this module, students will gain an understanding of common weaknesses in hardware implementation and become familiar with hardware and software mitigation techniques. Students will also learn hardware/software co-design to successfully mount the attacks. TOPICS: Hardware attack scenarios Hardware attack mitigation Timing attacks Power analysis Hardware fault classes Transient faults Sequential & combinatorial logic Common embedded protocols State machines Logical functions & arithmetic computation Logic optimization Security of CPLDs, FPGAs and ASICs Electronic test-equipment (oscilloscopes, logic analyzers) Secure design of computer architectures Hardware/software codesign

Module Components

Pflichtgruppe:

All Courses are mandatory.

Course NameTypeNumberCycleLanguageSWSVZ
HardwareSecurityVL0434 L 983WiSe/SoSeNo information2
Hardware Security LabPR0434 L 973SoSeNo information2

Workload and Credit Points

HardwareSecurity (VL):

Workload descriptionMultiplierHoursTotal
Exam Preparation1.015.0h15.0h
Preparation / Postprocessing15.03.0h45.0h
Presence Hours15.02.0h30.0h
90.0h(~3 LP)

Hardware Security Lab (PR):

Workload descriptionMultiplierHoursTotal
Final Report1.030.0h30.0h
Preparatory Studies (Online)1.030.0h30.0h
Presence Hours (Block)5.06.0h30.0h
90.0h(~3 LP)
The Workload of the module sums up to 180.0 Hours. Therefore the module contains 6 Credits.

Description of Teaching and Learning Methods

This module consists of a lecture and a practical course. Both courses will be taught in English. The practical course is held as a block course in a single week during the semester break. Attendance during these five days is mandatory!

Requirements for participation and examination

Desirable prerequisites for participation in the courses:

Prerequisites: - Compulsory modules of the Bachelor degree. - Experience with C programming Recommended additional skills: - Familiarity with HDL and logic design - Familiarity with electronics - Familiarity with test and measurement equipment For the practical course students will be provided access to workstations as well as test and measurement equipment used for the course.

Mandatory requirements for the module test application:

This module has no requirements.

Module completion

Grading

graded

Type of exam

Portfolio examination

Type of portfolio examination

No information

Language

English

Test elements

NamePoints/WeightCategorieDuration/Extent
(lab) final written report25No informationNo information
(lab) practical demo #15No informationNo information
(lab) practical demo #25No informationNo information
(lab) practical demo #35No informationNo information
(lab) practical demo #45No informationNo information
(lab) practical demo #55No informationNo information
(lecture) short oral exam50No informationNo information

Grading scale

No information

Test description (Module completion)

This module will be tested as a portfolio examination, i.e. you accumulate points during the course of the module for the following exam elemenst: • (Lecture) short consultation ("Rücksprache"): up to 50 points • (Practical Course) 5 practical demos: up to 5 points each • (Practical Course) final written report: up to 25 points The total number of points (0-100) is converted into a final grade according to Conversion Table 1 of School IV.

Duration of the Module

The following number of semesters is estimated for taking and completing the module:
2 Semester.

This module may be commenced in the following semesters:
Winter- und Sommersemester.

Maximum Number of Participants

The maximum capacity of students is 12.

Registration Procedures

Registration for the module through the examination office. The usual time restrictions on registrations for portfolio modules apply.

Recommended reading, Lecture notes

Lecture notes

Availability:  unavailable

 

Electronical lecture notes

Availability:  unavailable

 

Literature

Recommended literature
No recommended literature given

Assigned Degree Programs


This module is used in the following Degree Programs (new System):

Studiengang / StuPOStuPOsVerwendungenErste VerwendungLetzte Verwendung
This module is not used in any degree program.
Module applicable for CS Master (Communication-Based Systems), CE Master (Security & Dependability) and EE Master (elective).

Miscellaneous

No information