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Applied Embedded Systems Project

6 LP

English

#40335 / #4

Seit SS 2019

Fakultät IV

EN 12

Institut für Technische Informatik und Mikroelektronik

34341400 FG Architektur eingebetteter Systeme

Juurlink, Bernardus

Juurlink, Bernardus

aep@aes.tu-berlin.de

POS-Nummer PORD-Nummer Modultitel
62346 29153 Applied Embedded Systems Project

Learning Outcomes

Knowledge and practical experiences in the realm of designing embedded processor architectures and its programming are gained. Students are able to plan, coordinate and carry out hardware/software co-design, programming in hardware description languages and system-level programming, as well as team management and coordination in a project.

Content

In this module, a design and implementation assignment, embedded in a concrete, extensive, and challenging development project is to be solved self-reliantly in team work. This assignment conduces to apply gained methods and knowledge in the realm of computer architecture design and is connected to current research topics of the AES group. The study is to be done under as realistic and work-live compliant conditions as possible, including planning, design, implementation, management, coordination, and presentation of work and results of the concrete team work. Exemplary, the following topics are possible: - Map an embedded single-threaded application to an embedded multi-core platform. - Speed-up an application by using FPGA or GPU technology. - Speed-up an embedded system by analyzing and implementing processor and architecture extensions.

Module Components

Pflichtteil:

All Courses are mandatory.

Course Name Type Number Cycle Language SWS
Applied Embedded Systems Project (AEP) PJ 0433 L 231 SS No information 4

Workload and Credit Points

Applied Embedded Systems Project (AEP) (PJ):

Workload description Multiplier Hours Total
Weekly contact hours 15.0 4.0h 60.0h
Project documentation 1.0 15.0h 15.0h
Project presentation 1.0 15.0h 15.0h
Research, management, implementation, testing 15.0 6.0h 90.0h
180.0h(~6 LP)
The Workload of the module sums up to 180.0 Hours. Therefore the module contains 6 Credits.

Description of Teaching and Learning Methods

The project starts with an intensive research phase to analyze the capabilities of the used hardware components. This is followed by a planning and design phase. Most of the time, groups will implement and test their project idea. The project will be finished with a presentation including a demo and by writing a project documentation.

Requirements for participation and examination

Desirable prerequisites for participation in the courses

Basic knowledge about computer architecture is obligatory (e.g. Technische Grundlagen der Informatik 2 (TechGI2)). Desirable are practical experiences in hardware description languages, synthesis of hardware descriptions, as well as microcontroller or system-level programming.

Mandatory requirements for the module test application

No information

Module completion

Grading:

graded

Type of exam:

Portfolio examination

Language:

English

Typ of portfolio examination

100 points in total

Test elements

Name Points Categorie Duration/Extent
(Deliverable Assessment) Project documentation 20 written 15 pages
(Deliverable Assessment) Project implementation 60 practical 4 months
(Deliverable Assessment) Project presentation 20 oral 20 minutes

Grading scale

1.01.31.72.02.32.73.03.33.74.0
95.090.085.080.075.070.065.060.055.050.0

Test description (Module completion)

No information

Duration of the Module

This module can be completed in one semester.

Maximum Number of Participants

The maximum capacity of students is 30.

Registration Procedures

Pre-registration is organized via ISIS2 system. Registration for the exam is carried out on the examination office (possibly electronically via QISPOS) within the first six weeks of the semester.

Recommended reading, Lecture notes

Lecture notes

Availability:  unavailable

Electronical lecture notes

Availability:  unavailable

Literature

Recommended literature
ISIS2 system will be used to publish all course material.

Module examiner

Prüfungsberechtigte Personen im WS 2019/20: 4

Name
Herr Dr. Nicolai Bull (geb. Stawinoga)
Herr Dr.-Ing. Anselm Busse
Herr Biagio Cosenza
Herr Bernardus Juurlink

Assigned Degree Programs

Zur Zeit wird die Datenstruktur umgestellt. Aus technischen Gründen wird die Verwendung des Moduls während des Umstellungsprozesses in zwei Listen angezeigt.

This module is used in the following modulelists:

- Masterstudiengang Technische Informatik: Studienschwerpunkte: Rechnertechnik, Technische Anwendungen - Masterstudiengang Elektrotechnik: Ergänzungsmodul - Masterstudiengang ICT Innovation Embedded Systems (Pflichtmodul im 1. Semester)

This module is used in the following Degree Programs (new System):

    - Masterstudiengang Technische Informatik: Studienschwerpunkte: Rechnertechnik, Technische Anwendungen - Masterstudiengang Elektrotechnik: Ergänzungsmodul - Masterstudiengang ICT Innovation Embedded Systems (Pflichtmodul im 1. Semester)

    Miscellaneous

    No information