Learning Outcomes
To become familiar with the architecture and organization of recent superscalar and VLIW processors and multicores.
To be able to select, given functional and non-functional requirements, the most appropriate computer architecture.
To be able to optimize code for a particular processor using, e.g., code scheduling and loop unrolling.
To become familiar with parallel computer architectures, cache coherence, memory consistency, etc.
To be able to design a memory hierarchy that optimizes latency, throughput, and or energy dissipation.
To be able to study recent advances in computer architecture, classify recent research articles, and report about it, both verbally and in writing.
